Semiconductors & Microelectronics Solid-state physics through the integrated circuit to modern fabs — the pioneers, the paradigms, the scaling limits
A mind map of semiconductors and microelectronics: the solid-state physics foundations; the transistor breakthrough; the integrated circuit and the planar process; microprocessors, memory, and logic; lithography from contact printing to EUV; the fabless-foundry revolution; and the scaling laws, physical limits, and geopolitics that define the modern industry. Named inventors, labs, processes, and products with dates across six branches.
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Physics & the Transistor Integrated Circuit & Planar Process Microprocessors, Memory & Logic Lithography & Process Nodes Fabless-Foundry Model Scaling Laws, Limits & Geopolitics Solid-state physics foundations Materials and crystal growth The 1947 breakthrough Shockley Semiconductor and the Traitorous Eight MOS and the field-effect transistor The IC race The planar process Fairchild's spinoff cascade Process innovations Other early players The microprocessor era The RISC insurgency DRAM, SRAM, and flash Japanese DRAM rise and fall Accelerators: GPU, TPU, NPU Photolithography generations EUV lithography Process nodes — historical and marketing Advanced transistors Interconnect and packaging TSMC and the foundry birth Fabless design houses IDM survivors and pivots The equipment and materials chain Mead-Conway and the design revolution The named laws Physical limits Economic structure Tradeoffs that define the field Geopolitics and policy Karl Ferdinand Braun — crystal rectification, 1874 Edwin Hall — Hall effect, Johns Hopkins 1879 Julius Edgar Lilienfeld — first FET patent, 1925 (not built) Oskar Heil — field-effect patent, 1934 Felix Bloch — electron wave states in crystals, 1928 (Bloch theorem) Alan Wilson — band theory of semiconductors, Cambridge 1931 Boris Davydov — p-n junction theory, USSR 1938 (undercredited) Walter Schottky — metal-semiconductor barrier, 1938 Russell Ohl — silicon p-n junction at Bell Labs, 1940 Gordon Teal & Morgan Sparks — zone refining for pure germanium, Bell Labs 1950 Teal — single-crystal silicon growth, Texas Instruments 1954 Jack Scaff — crystal purification methods during WWII Bell Telephone Laboratories Solid State Physics Group formed, 1945 William Shockley leads the group — Mervin Kelly sanctions it John Bardeen & Walter Brattain demonstrate point-contact transistor, Dec 23, 1947 Germanium, two gold foil contacts, an OA amplifying triode Shockley — junction (bipolar) transistor theory, 1948 Shockley — Electrons and Holes in Semiconductors textbook, 1950 Nobel Prize in Physics, 1956 — Shockley, Bardeen, Brattain Name "transistor" coined by John R. Pierce at Bell Labs, 1948 Shockley Semiconductor Laboratory — Mountain View, CA 1955 Shockley's management style drives eight engineers to quit, 1957 The Traitorous Eight: Moore, Noyce, Hoerni, Last, Grinich, Roberts, Kleiner, Blank Fairchild Semiconductor founded, Sep 1957 ($3,600 each in seed) Arthur Rock arranges Fairchild Camera & Instrument funding Mohamed Atalla & Dawon Kahng — MOSFET demonstration, Bell Labs 1959 CMOS invented by Frank Wanlass at Fairchild, 1963 Wanlass & Sah — "Nanowatt Logic Using Field-Effect MOS Triodes," 1963 Herbert Kroemer — heterostructure transistor theory, 1957 (Nobel 2000, undercredited) Jack Kilby — germanium IC demo at Texas Instruments, Sep 12, 1958 Kilby patent — Miniaturized Electronic Circuits, filed Feb 1959 Robert Noyce — monolithic silicon IC concept, Fairchild, Jan 1959 Noyce patent — Semiconductor Device-and-Lead Structure, Apr 1961 Kilby-Noyce cross-licensing agreement, 1966 Nobel Prize in Physics, 2000 — Kilby (Noyce died 1990) Jean Hoerni — planar process at Fairchild, 1959 SiO2 passivation layer — the key enabler Planar process makes Noyce's monolithic IC manufacturable Photolithography with photoresist — Lathrop & Nall at Diamond Ordnance Fuze Lab, 1957 Bob Schweikert — first working planar IC at Fairchild, 1960 Jean Hoerni, Jay Last, Eugene Kleiner leave Fairchild, 1961 (Amelco) Charlie Sporck leaves Fairchild for National Semiconductor, 1967 Jerry Sanders and others leave for AMD, 1969 Moore & Noyce leave to found Intel, Jul 1968 Don Hoefler — "Silicon Valley USA" Electronic News articles, 1971 ~65 companies tracked back to Fairchild alumni — the "Fairchildren" Beam-lead technology — Bell Labs 1960s Silicon-on-insulator (SOI) concept — 1960s Ion implantation — early 1970s commercial adoption Self-aligned gate — Federico Faggin at Fairchild, 1968 Silicon-gate technology enables the 4004 microprocessor Texas Instruments TTL 7400 series — 1964 (industry-standard logic) Motorola Semiconductor founded, 1955 RCA CMOS 4000 series — 1968 Mostek 4096 DRAM — 1973 (introduces address multiplexing) Intel 4004 — Ted Hoff, Federico Faggin, Stanley Mazor, Masatoshi Shima, Nov 1971 4-bit, 2,300 transistors, 10 μm process, 740 kHz Intel 8008 — 8-bit, 1972 (commissioned by Datapoint) Intel 8080 — 1974 (the first dominant microprocessor) Motorola 6800 — 1974; MOS 6502 — Chuck Peddle, 1975 ($25 price point) Zilog Z80 — Faggin + Shima, 1976 Intel 8086 — 1978 (founds x86 architecture) John Cocke — IBM 801 RISC, 1974–1980 David Patterson — Berkeley RISC I, 1981 John Hennessy — Stanford MIPS, 1981 ARM — Acorn RISC Machine, Cambridge 1985 SPARC — Sun Microsystems, 1987 RISC-V — open ISA from Berkeley, 2010 Robert Dennard — 1T-1C DRAM cell, IBM 1966–1968 Intel 1103 DRAM — 1 Kbit, 1970 (first commercial DRAM) SRAM cell — six-transistor, used for caches Fujio Masuoka — NOR flash at Toshiba, 1980; NAND flash, 1987 3D NAND — Samsung V-NAND, 2013; 200+ layers by 2024 HBM (High Bandwidth Memory) — SK Hynix / AMD, 2013 CXL (Compute Express Link) — 2019 consortium standard VLSI Project — MITI-funded Japanese consortium, 1976–1980 Hitachi, NEC, Fujitsu, Toshiba, Mitsubishi as "Big Five" Japan captures 80% of DRAM market by 1986 US-Japan Semiconductor Agreement, 1986 — quotas and floor prices Intel exits DRAM, 1985 — pivots to microprocessors Sematech founded, 1987 — US industry-government consortium Samsung becomes #1 DRAM producer, 1993 — Korea displaces Japan NVIDIA founded — Jensen Huang, Chris Malachowsky, Curtis Priem, 1993 NVIDIA GeForce 256 — first "GPU" branding, 1999 CUDA — parallel computing platform, 2006 Google TPU v1 — 2015, announced 2016 (inference-focused) NVIDIA H100 — Hopper architecture, 80GB HBM3, 2022 NVIDIA Blackwell B200 — 2024 Cerebras wafer-scale engine — 2019 (single 46,225 mm² die) Groq LPU, Tenstorrent, Graphcore — specialized AI silicon Contact printing — 1960s (photoresist + mask direct contact) Proximity printing — 1970s Projection printing — 1973 (Perkin-Elmer Micralign) Step-and-repeat (steppers) — GCA, 1978 I-line (365nm) lithography — 1980s dominant KrF excimer laser (248nm) — 1990s dominant ArF excimer laser (193nm) — 2000s dominant Immersion ArF (193i) — water between lens and wafer, 2004 Double / quad patterning — 2010s workarounds ASML — Dutch spinoff from Philips, 1984 EUV wavelength: 13.5nm (soft X-ray) EUV source — Sn droplet hit by CO2 laser, 50kW TSMC N7+ uses EUV, 2019 — first volume EUV node High-NA EUV (0.55 NA) — TWINSCAN EXE:5000, 2024 ASML EXE:5000 costs ~$380M per tool Only ASML makes EUV — load-bearing chokepoint 10 μm (4004, 1971) → 3 μm (1980s) → 1 μm (1988) 180nm (1999) — early CMOS scaling era 90nm (2004) — when Dennard scaling effectively ends 45nm (2007) — Intel introduces high-k metal gate 22nm (2012) — Intel FinFET (Tri-Gate) first 14nm / 10nm / 7nm — naming decouples from gate length 5nm (TSMC N5, 2020) — first volume EUV 3nm (TSMC N3, 2022) — FinFET limit; Samsung uses GAA 2nm nanosheet GAA (TSMC N2, 2025; Samsung SF2) FinFET — Chenming Hu group at Berkeley, 1999 Intel 22nm Tri-Gate — first commercial FinFET, 2011 Gate-all-around (GAA) nanosheet — Samsung 3GAE, 2022 Complementary FET (CFET) — post-2030 roadmap High-k metal gate — HfO2 dielectric replaces SiO2, 2007 Copper interconnect — IBM introduces, 1997 (replaces aluminum) Low-k dielectrics — SiOF, SiOC to reduce capacitance 2.5D packaging — TSMC CoWoS (Chip-on-Wafer-on-Substrate), 2011 3D packaging — through-silicon vias (TSV), HBM stacks Intel Foveros 3D stacking, 2019 Chiplets / UCIe open interconnect standard, 2022 AMD MI300A/X — first volume CPU+GPU chiplet APU, 2023 Morris Chang — recruited by Taiwanese government from TI, 1985 TSMC founded — 1987, with ITRI and Philips capital Pure-play foundry — no products of its own, only manufacturing TSMC IPOs in Taiwan (1993) and ADR (1997) TSMC market cap surpasses Intel, 2020 TSMC Arizona fab — 4nm, announced 2020, first production 2025 Cypress Semiconductor, LSI Logic, Cirrus Logic — early fabless, 1980s Qualcomm — founded 1985; mobile modem dominance Broadcom — founded 1991 NVIDIA — fabless from founding, 1993 AMD goes fabless — spins off GlobalFoundries, 2009 Apple M-series — ARM-based, TSMC-fabricated, 2020 Intel — IDM dominant until ~2015; struggles with 10nm 2015–2021 Intel IDM 2.0 — Pat Gelsinger's return and foundry ambition, 2021 Samsung — memory leader, logic foundry since 2005 SK Hynix — DRAM and NAND; HBM leadership 2020s Micron Technology — founded 1978, DRAM + NAND Texas Instruments — pivots from logic to analog leadership, 1990s ASML — EUV lithography monopoly Applied Materials — deposition, etch, CMP Lam Research — etch and deposition KLA — metrology and inspection Tokyo Electron — tracks, etch, cleaning Shin-Etsu, SUMCO — silicon wafer duopoly JSR, Tokyo Ohka, Shin-Etsu — photoresist oligopoly Carver Mead — Introduction to VLSI Systems textbook, 1980 Lynn Conway — structured VLSI design methodology, Xerox PARC 1978 MOSIS — multi-project wafer service, 1981 (academic access to fabs) Synopsys — founded 1986, logic synthesis leader Cadence — founded 1988, physical design tools EDA industry: Synopsys, Cadence, Siemens EDA (Mentor) Moore's Law — Gordon Moore, Electronics magazine, Apr 1965 Moore's 1975 revision — doubling every 2 years Dennard scaling — Robert Dennard et al., IEEE JSSC 1974 Koomey's Law — performance per joule doubles every ~1.57 years, 2010 Wright's Law applied to cost per transistor — continues even as density slows Rock's Law — cost of a fab doubles every 4 years Makimoto's Wave — 10-year cycle between standard and custom silicon Huang's Law — GPU performance doubles every ~2 years (informal) Subthreshold slope floor — 60 mV/decade at 300K (Boltzmann limit) Dennard scaling breakdown ~2005 — power density plateaus Quantum tunneling at gate oxides thinner than ~1.2nm Wire RC delay dominates beyond 10nm SRAM cell scaling effectively stops ~3nm Single-atom dopant variability at extreme nodes Landauer limit — kT ln 2 per irreversible bit erasure Leading-edge fab cost ~$20B (TSMC N2, 2025) Leading-edge mask set ~$50M at 3nm Fewer than 3 companies at the leading edge by 2025: TSMC, Samsung, Intel Mature-node foundries: SMIC, UMC, GlobalFoundries, TSMC mature Semiconductor industry revenue ~$600B, 2024 Industry concentration — top 10 firms >60% of revenue Performance vs. power — the post-Dennard multicore pivot Density vs. yield — smaller transistors harder to make reliably Integration (IDM) vs. specialization (fabless/foundry) General-purpose CPU vs. domain-specific accelerator Monolithic vs. chiplet — cost vs. yield tradeoff Memory bandwidth vs. compute — the "memory wall" Shoreline length vs. die area — packaging constraint US Entity List additions — Huawei 2019, SMIC 2020 US export controls on advanced chips — Oct 2022 BIS rules Revised controls Oct 2023; further tightened 2024 EU Chips Act — 2023 (€43B target) US CHIPS and Science Act — Aug 2022 ($52B) TSMC Arizona, Samsung Austin, Intel Ohio fabs ASML DUV sales restrictions to China, 2023 Japan's Rapidus — 2nm fab ambition, Hokkaido, with IBM partnership Taiwan "Silicon Shield" doctrine Semiconductors & Microelectronics Brian Tighe · Mind Maps Orbital mind map. Scroll to zoom, drag to pan, or use the buttons above (+ / − / 0 keys also work). Hover a node to highlight its path to the center and the subtree beneath it. How to read this The center holds the topic. The six branches fan out bilaterally — three on each side — each in its own color. Sub-branches nest three levels deep under each top-level branch. Hover a leaf to trace the path back to the center; hover a branch to see everything it contains.
This is the shape the topic has when you try to hold the whole field in your head at once. It is not an argument; it is a scaffold. The essays argue against or within scaffolds like this one.